The K1-16/16 Computer

Last updated: 2009-11-08
Questions & comments to Kio

The Project

Sometimes you are struck by an idea...

Due to depressions programming became harder and harder. So i thought, why don't do something more simple, with more manual work? Electronics, for instance. And, thanks to the internet, i have already read from other maniacs, who built a 6502 CPU. Or a Z80 in FPGA. Or Dennis Kuschel's myCPU. And there's a web ring about it. If others can do this, it can't be that hard. Basically...

Of course my CPU should be Different. Better. And Simple, so that i can understand it myself. B-)

For symmetry i settled with a 16/16 bit design: 16 data bits and 16 address bits.

Unusual and Generally Interesting Parameters

K1-16/16 CPU

• Combined Harvard and Von Neumann architecture
• 16 MHz system clock
Front panel with slow motion clock for exhibitions et. al.
Full static design down to 0 Hz
• 16 bit internal data bus
• 16 bit internal address bus
• 64k x 16 bit internal ram
• 32k x 24 bit microcode
organized as 2 code planes à 16k for conditional execution and branching.
the microcode is copied from eproms to rams during boot.
this is used to increase the clock speed of the control unit.
it should also be possible to load the microcode from an external source instead.
• No flag register. (but flags)
• Built with discrete logics using 74HCxx and 74ACxx ICs
CPU fits on 5 "Euro" printed circuit boards (160 x 100mm)
• Manual circuit design
Mostly manual routing of the PCBs (with EagleCAD)
Professional made double-layer circuit boards

K1-Bus

• 16 bit expansion bus
• Up to 16 expansion boards with individual interrupts and priority
• Up to 32 MByte/sec data transfer capability

Harvard Architecture

Programs can be written directly in microcode. Adopting this view, the K1 CPU has separated program and data memory. This is the Harvard Architecture.

Von Neumann Architecture

More likely, the CPU can also use a fixed microcode, which reads opcodes from the ram and executes them. Seen this way it has a combined program and data memory. This is the Von Neumann Architecture.

Project Log

2008

Planning. Design and evaluation of circuits. First i drew the PCBs in Freehand, a graphics program. But Freehand was bought by Adobe and Adobe terminated development. So i bought a non-profit license for the circuit design and layout program from CadSoft, which is quite affordable.

2009

EagleCAD certainly has it's quirks.

2009-01

Production of the first board by PCB-Pool (voucher). It is the control unit, which is abbreviated as "SSW" for German "Schrittschaltwerk".

2009-02

I'm in the Homebuilt CPU Webring.

The Control Unit is finished:

2009-03

Working on the microcode and microcode assembler.

The microcode is organized in 2 planes of 16k * 24-bit codes. There is a 1-instruction pipeline which imposes a 1-instruction latency on code branching: In every microcode instruction a flag is selected. This flag is tested at the end of the previous instruction and determines from which code plane the next instruction is read. The assembler takes care for the most of this brain hazzard.

2009-04:

Working on the compiler for user-space (as opposed to microcode) programs. It seems it's gonnabe a compiler, not an assembler, with c-like syntax and some c++ goodies. Finally i got stuck. Using a non-typed script language to write a compiler has it's disadvantages too.

2009-08:

After a long while I resumed work on the Arithmetic/Logic Unit. I wired up a test circuit for the 3-resistor majority gate, which i use in the ALU for the joined AND and OR functions. I was lucky and the gate worked as expected. Dieter Müller has written an article about the majority gate and it's use for ALU design.

2009-09:

I finished and manufactured the front panel PCB. It provides 3 clock sources for demonstrations and debugging. It is single-sided, so i could etch it at home. I have tested my mental rugginess and designed the front panel in Open Office.

2009-09-27: Today we had elections in Germany. Of course i did vote, though, there is not much to choose between ...

2009-10:

2009-10-05: CadSoft is bought by Premier Farnell plc.

I have ordered the ALU PCB from LeitOn.
It is of lower quality than the board from PCB-Pool.

2009-11:

I have ordered the address and data registers boards from LeitOn. Again the quality is not as good as from PCB-Pool, the boards are slightly bent. Both boards are now finished:

Project State [2009-11]

The control unit, ALU and frontpanel PCB are produced.
DRegs and ARegs PCBs arrived. [2009-11-03]
DRegs and ARegs boards are finished. [2009-11-07]
The I/O board is under development.
I am reworking the project pages.

Name	Letzte Änderung	Länge
Case/	2009-11-06 16:31	7
Data Sheets/	2009-02-23 17:18	28
Images/	2009-11-06 16:20	2
IO-Boards/	2009-11-06 16:23	1
K1-Bus/	2009-09-20 11:26	18
K1-CPU 16-16/	2009-11-08 09:46	12
K1-CPU/	2009-11-06 15:13	13
Software/	2009-10-11 17:14	3